1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as drain and source regions, are connected to the metallization system of the semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain and a source.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor elements but the electrical performance of the complex wiring fabric, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, in order to establish a connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the metallization layer. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have to be provided with appropriate critical dimensions on the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and, thus, the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy. For this reason, frequently, contact trenches or contact bars are formed in the interlayer dielectric material in order to connect to the corresponding drain and source areas along a significant portion or the entire width of transistor devices. In some sophisticated techniques, the contact bars are formed in a first portion of the interlayer dielectric material and connect to the drain and source contact areas, while, on the other hand, a height of the contact bars is restricted to approximately the height of the gate electrode structures in order to not unduly increase the overall fringing capacitance. That is, any gate electrode structures may, for instance, be connected by appropriate contact elements or vias, which in turn may connect to a metallization system to be formed above the circuit elements. On the other hand, the contact bars may connect to appropriately positioned and dimensioned metal lines, frequently formed of a highly conductive material, such as copper and the like, which in turn may be contacted by appropriate vias that establish the vertical connection to the actual metallization system of the semiconductor device. The metal lines for connecting to the contact bars, which are frequently referred to as metal lines of a metal zero level, have to be provided with an appropriately adapted bottom width, in particular in densely packed device areas, since here the self-aligned contact bars may have a top width of approximately 50 nm and significantly less, wherein, in sophisticated applications, even a top width of the contact bars may be 20 nm and less. On the other hand, a top width of these metal zero metal lines may have to provide sufficient margins in order to enable a reliable “landing” of vias as vertical contacts for connecting to the metallization system. Consequently, in conventional strategies, the corresponding openings in the dielectric material of the metal zero level may be formed with appropriate etch strategies, in which extremely steep sidewall angles are achieved, which, however, may also result in a reduced top critical dimension, while at the same time the overall control of the critical dimensions is significantly reduced. On the other hand, applying any etch strategies in which a pronounced tapering is achieved so as to provide a sufficient top critical dimension while also complying with an extremely small bottom critical dimension may result in pronounced patterning-related non-uniformities, thereby contributing to a pronounced yield loss in this manufacturing stage.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which a contact regime for connecting to contact bars, in particular in densely packed device areas, may be provided, while avoiding or at least reducing the effects of one or more of the problems identified above.